This invention relates generally to data processing systems including a central processor unit (CPU) and a random access memory (RAM) and is particularly directed to an arrangement for directly reading data from a dynamic random access memory (DRAM) to the CPU up to the end of a memory access cycle regardless of the length of the cycle.
In data processing systems, the CPU typically gains access to the system's RAM by asserting a READ or WRITE pulse for respectively reading data already stored in the RAM or storing new data in the RAM. The READ/WRITE pulse is frequently asserted early in the RAM access cycle and terminates at the end of the cycle such that valid data may be transmitted between the CPU and RAM up to the end of the access cycle. Moreover, the transfer of data between the CPU and RAM may be asynchronous such that the data may be transmitted at any time during the access cycle and may take place only over a very short period of time or may last for a substantial portion of the cycle, even extending beyond the end of a cycle.
A memory controller is typically provided in such data processing systems for generating control signals in response to the output of a READ/WRITE pulse from a processor such as a CPU or a direct memory access (DMA) controller. Addresses are generated in the processor to access a predetermined data storage location in the RAM. The organization of the RAM is typically in the form of a matrix, with each data storage location identified by a unique combination of a row address and a column address. A row address strobe (RAS) signal and a column address strobe (CAS) signal are provided to the RAM and function as enabling clock signals for introducing row and column address information into the RAM. More specifically, in the case of dynamic random access memories (DRAMs), the CAS signal latches column address information into the DRAM on its active going edge. Once the CAS signal is active, it serves as an output enable for the DRAM during a read cycle. Most DRAMs are specified such that when the CAS signal goes inactive in a read cycle, the data output from it can go invalid immediately.
DRAMs are used in many applications because of their large memory capacity, high operating speeds, and low cost. In spite of these advantages, problems have been encountered in data transfer systems employing a DRAM. For example, where memory access is asynchronous and valid data is provided to the end of the memory access cycle, the READ or WRITE pulse cannot be used to directly generate the RAS or CAS pulse for the DRAM because the minimum time between the end of a first READ/WRITE pulse and the start of a second, or next, READ/WRITE pulse may be less than the precharge time required by the DRAM. The DRAM's precharge time represents the time interval after the address strobe goes inactive until the occurrence of an access signal by the DRAM and before the next column/row information may be strobed into the DRAM and arises from the requirement to fully charge the various devices within the DRAM following the occurrence of a first memory access and before the next subsequent memory access. If allowance is not made for the precharge time, the data which the CPU attempts to either read from or write into the DRAM may be lost.
To address this DRAM operating limitation, prior art approaches have made use of the leading edge of the READ/WRITE pulse to initiate the start of an access cycle and to generate subsequent DRAM timing signals using fixed time delays from the leading edge of the READ/WRITE pulse. This approach allows the end of the RAS pulse to occur before the end of the READ/WRITE pulse and permits the RAS precharge time to be accommodated. However, this solution does not eliminate the problem since the CAS signal may now terminate before the end of the READ/WRITE pulse resulting in invalid data being available when the CPU requires it.
This is best shown in FIG. 1 which illustrates the timing of the various aforementioned signals in a prior art data processing system. With all of the sgnals being active low, a memory access cycle is initiated by the leading edge of a READ pulse which occurs at time t.sub.o. Following a predetermined interval t.sub.1 as determined by a DRAM controller, a RAS pulse is provided to the DRAM for designating the row address from which data is to be read from the DRAM. Following a second time interval after the occurrence of the leading edge of the RAS pulse (t.sub.2 -t.sub.1), a CAS pulse is provided to the DRAM for designating the column address from which the desired data is to be read. During the CAS pulse, the data is read by the CPU from a given location in the DRAM. In the aforementioned prior art approach, the end of the CAS pulse could occur before the end of the READ pulse. However, with the CAS pulse and thus the time during which valid data is available for reading from the DRAM by the CPU terminating at time t.sub.4 and thus prior to the end of the READ pulse at t.sub.5, the CAS signal ends before the end of the READ pulse and thus data could be invalid when the CPU requires it.
This problem has been addressed in the prior art by the use of latches coupled between the DRAM and CPU for latching data at the end of the CAS pulse so that the data at the DRAM need not be valid at the end of an access cycle since it is latched by external components. Once latched, the data is then provided to the CPU. These latching components, however, increase data processing system complexity as well as its cost and require additional printed circuit PC board surface area for mounting in an environment where space is always at a premium.
In addition, with the aforementioned latches introducing a fixed delay following the leading edge of the READ/WRITE pulse in generating subsequent DRAM timing signals, signal timing problems may occur when the DRAM is accessed in turn by two or more devices having different operating speeds. For example, the DRAM may be accessed by a CPU, a DMA controller, an I/O processor, etc., all of which may have different characteristic operating speeds. With the aforementioned fixed delay established by the speed of the fastest memory access device, which typically is the main processor or CPU, improper timing between the READ/WRITE pulse and the RAS and CAS pulses may occur when one of the memory access devices for which the fixed delay is not optimized is accessing the DRAM resulting in the reading of invalid data into the DRAM.
The present invention overcomes the aforementioned limitations of prior art approaches by allowing for the transfer of data between a plurality of memory access devices each having a different characteristic operating speed and a high speed DRAM up to the end of a memory access cycle without the use of external data latches so as to prevent the loss of valid data.